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CY62128BN MoBL(R)
1-Mbit (128K x 8) Static RAM
Features
* Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive-A: -40C to 85C -- Automotive-E: -40C to 125C * 4.5V-5.5V operation * CMOS for optimum speed/power * Low active power (70 ns Commercial, Industrial, Automotive-A) -- 82.5 mW (max.) (15 mA) * Low standby power (55/70 ns Commercial, Industrial, Automotive-A) -- 110 W (max.) (15 A) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options * Available in Pb-free and non-Pb-free 32-pin (450 mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I
Functional Description[1]
The CY62128BN is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Logic Block Diagram Pin Configuration
Top View SOIC
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GN G g gnc GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE 2 WE A13 A8 A9 A11 OE A10 CE 1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8
I/O 0 I/O 1
ROW DECODER
SENSE AMPS
I/O 2 I/O 3 I/O 4 I/O 5
128K x 8 ARRAY
CE1 CE2 WE OE
COLUMN DECODER
POWER DOWN
I/O 6 I/O 7
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-06498 Rev. *A
A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006
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CY62128BN MoBL(R)
Product Portfolio
Power Dissipation VCC Range (V) Product CY62128BNLL Commercial Industrial Automotive-A Automotive-E Min. 4.5 Typ.[2] 5.0 Max. 5.5 Speed (ns) 55 70 55 70 70 70 Operating, ICC (mA) Standby, ISB2 (A) Typ.[2] Max. Typ.[2] Max. 7.5 6 7.5 6 6 6 20 15 20 15 15 25 2.5 2.5 2.5 2.5 2.5 2.5 15 15 15 15 15 25
Pin Configurations
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
STSOP Top View (not to scale)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP I Top View (not to scale)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
Pin Definitions
Input Input/Output Input/Control Input/Control Input/Control Input/Control Ground A0-A16. Address Inputs I/O0-I/O7. Data lines. Used as input or output lines depending on operation WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. CE1. Chip Enable 1, Active LOW. CE2. Chip Enable 2, Active HIGH. OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins GND. Ground for the device
Power Supply VCC. Power supply for the device
Note: 2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production variations as measured at VCC = 5.0V, TA = 25C, and tAA = 70 ns.
Document #: 001-06498 Rev. *A
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CY62128BN MoBL(R)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND
[3]
Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Commercial Industrial Automotive-A Automotive-E Ambient Temperature (TA)[4] 0C to +70C -40C to +85C -40C to +85C -40C to +125C VCC 5V 10%
.... -0.5V to +7.0V
DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V DC Input Voltage[3] .................................-0.5V to VCC + 0.5V Current into Outputs (LOW) .........................................20 mA
Electrical Characteristics Over the Operating Range
-55 Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Input HIGH Voltage Input LOW Voltage[3] Input Leakage Current GND VI VCC Commercial/ Industrial Automotive-A Automotive-E IOZ Output Leakage Current GND VI VCC, Output Disabled Commercial/ Industrial Automotive-A Automotive-E ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Commercial/ Industrial Automotive-A Automotive-E ISB1 Automatic CE Max. VCC, CE1 VIH Commercial/ Power-down Current or CE2 < VIL, Industrial --TTL Inputs VIN VIH or Automotive-A VIN VIL, f = fMAX Automotive-E Automatic CE Max. VCC, Power-down Current CE1 VCC - 0.3V, or CE2 0.3V, --CMOS Inputs VIN VCC - 0.3V, or VIN 0.3V, f = 0 Commercial/ Industrial Automotive-A Automotive-E 0.1 2 7.5 20 -1 +1 Test Conditions VCC = Min., IOH = -1.0 mA Min. 2.4 0.4 2.2 -0.3 -1 VCC + 0.3 0.8 +1 2.2 -0.3 -1 -1 -10 -1 -1 -10 6 6 6 0.1 0.1 0.1 2.5 15 2.5 2.5 2.5 Typ.[2] Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 +10 +1 +1 +10 15 15 25 1 1 2 15 15 25 -70 Typ.[2] Max. Unit V V V V A A A A A A mA mA mA mA mA mA A A A
Output LOW Voltage VCC = Min., IOL = 2.1 mA
ISB2
Notes: 3. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 4. TA is the "Instant On" case temperature.
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CY62128BN MoBL(R)
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9 9 Unit pF pF
Thermal Resistance[5]
Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 32 SOIC 66.17 30.87 32 STSOP 105.14 14.09 32 TSOP 97.44 26.05 Unit C/W C/W
JA JC
AC Test Loads and Waveforms
5V OUTPUT 100 pF INCLUDING JIG AND SCOPE (a) R2 990 R1 1800 R1 1800 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 990 GND Rise TIme: 1 V/ns Equivalent to: THEVENIN EQUIVALENT 639 1.77V OUTPUT VCC ALL INPUT PULSES 90% 10% 90% 10%
Fall TIme: 1 V/ns
Data Retention Waveform
DATA RETENTION MODE VDR > 2V
VCC
CE1
VCC, min. tCDR
VCC, min. tR
or CE2
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = VDR = 2.0V, CE1 VCC - 0.3V, or CE2 0.3V, VIN VCC - 0.3V or, VIN 0.3V Commercial/ Industrial Automotive-A Automotive-E tCDR Chip Deselect to Data Retention Time 0 70 Conditions[6] Min. 2.0 1.5 15 Typ. Max. Unit V A
1.5
25
A ns ns
Operation Recovery Time tR Note: 5. Tested initially and after any design or process changes that may affect these parameters. 6. No input may exceed VCC + 0.5V.
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CY62128BN MoBL(R)
Switching Characteristics[7] Over the Operating Range
CY62128BN-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[7, 9] CE1 LOW to Low Z, CE2 HIGH to Low Z[9] CE1 HIGH to High Z, CE2 LOW to High Z[8, 9] 0 55 55 45 45 0 0 45 25 0 5 20 70 60 60 0 0 50 30 0 5 25 CE1 LOW to Power-up, CE2 HIGH to Power-up CE1 HIGH to Power-down, CE2 LOW to Power-down
[10]
CY62128BN-70 Min. 70 Max. Unit ns 70 5 70 35 0 25 5 25 0 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description
Min. 55
Max.
55 5 55 20 0 20 5 20
Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[9] Z[8, 9]
Switching Waveforms
Read Cycle No.1[11, 12]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 12. WE is HIGH for read cycle.
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CY62128BN MoBL(R)
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Write Cycle No. 1 (CE1 or CE2 Controlled)[14, 15]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
Notes: 13. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 14. Data I/O is high impedance if OE = VIH. 15. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY62128BN MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD
Write Cycle No.3 (WE Controlled, OE LOW)[14, 15]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tSD DATAI/O NOTE 16 tHZWE
Note: 16. During this period the I/Os are in the output state and input signals should not be applied.
tHA tPWE
tHD
DATA VALID tLZWE
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CY62128BN MoBL(R)
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0-I/O7 High Z High Z Data Out Data In High Z Power-down Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 Ordering Code CY62128BNLL-55SC CY62128BNLL-55SXC CY62128BNLL-55SI CY62128BNLL-55SXI CY62128BNLL-55ZAI CY62128BNLL-55ZAXI CY62128BNLL-55ZI CY62128BNLL-55ZXI 70 CY62128BNLL-70SC CY62128BNLL-70SXC CY62128BNLL-70ZC CY62128BNLL-70ZXC CY62128BNLL-70SI CY62128BNLL-70SXI CY62128BNLL-70ZAI CY62128BNLL-70ZAXI CY62128BNLL-70ZI CY62128BNLL-70ZXI CY62128BNLL-70ZXA CY62128BNLL-70SXA CY62128BNLL-70SXE CY62128BNLL-70ZAXE 51-85056 51-85081 51-85081 51-85094 51-85056 51-85094 51-85081 51-85056 51-85081 51-85056 51-85094 Package Diagram 51-85081 Package Type 32-pin 450-Mil SOIC 32-pin 450-Mil SOIC (Pb-Free) 32-pin 450-Mil SOIC 32-pin 450-Mil SOIC (Pb-Free) 32-pin STSOP 32-pin STSOP (Pb-Free) 32-pin TSOP Type I 32-pin TSOP Type I (Pb-Free) 32-pin 450-Mil SOIC 32-pin 450-Mil SOIC (Pb-Free) 32-pin TSOP Type I 32-pin TSOP Type I (Pb-Free) 32-pin 450-Mil SOIC 32-pin 450-Mil SOIC (Pb-Free) 32-pin STSOP 32-pin STSOP (Pb-Free) 32-pin TSOP Type I 32-pin TSOP Type I (Pb-Free) 32-pin TSOP Type I (Pb-Free) 32-pin 450-Mil SOIC (Pb-Free) 32-pin 450-Mil SOIC (Pb-Free) 32-pin STSOP (Pb-Free) Automotive-E Automotive-A Industrial Commercial Industrial Operating Range Commercial
Please contact your local Cypress sales representative for availability of these parts
Document #: 001-06498 Rev. *A
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CY62128BN MoBL(R)
Package Diagrams
32-pin (450 Mil) Molded SOIC (51-85081)
16 1
0.546[13.868] 0.566[14.376]
0.440[11.176] 0.450[11.430]
17
32
0.793[20.142] 0.817[20.751]
0.006[0.152] 0.012[0.304]
0.101[2.565] 0.111[2.819]
0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990]
0.050[1.270] BSC.
0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE
51-85081-*B
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CY62128BN MoBL(R)
Package Diagrams (continued)
32-pin STSOP (8 x 13.4 mm) (51-85094)
51-85094-*D
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CY62128BN MoBL(R)
Package Diagrams (continued)
32-pin TSOP Type I (8 x 20 mm) (51-85056)
51-85056-*D
All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62128BN MoBL(R)
Document History Page
Document Title: CY62128BN MoBL(R) 1-Mbit (128K x 8) Static RAM Document Number: 001-06498 REV. ** *A ECN NO. 426503 488954 Issue Date See ECN See ECN Orig. of Change NXR NXR New Data Sheet Added Automotive product Removed RTSOP Package Updated ordering Information table Description of Change
Document #: 001-06498 Rev. *A
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